This invention relates to integrated circuits such as programmable logic devices (“PLDs”), and more particularly to serial data signal interface or transceiver circuitry for use on PLDs or similar circuitry.
There is increasing interest in using high-speed serial data signals for communication between various devices in systems. For example, the devices in a system may be various integrated circuits that are mounted on a printed circuit board (“PCB”). The high-speed serial communication between the devices in such a system may take place via circuit traces on the PCB. One or more of the devices may be a PLD or that general type of relatively general-purpose, programmable or configurable device. All such devices to which the invention can be applied may sometimes be referred to generically as PLDs. This terminology is employed solely for convenience and is not intended to limit the invention to any particular narrow class of devices.
There are many communication protocols that are known for use in high-speed serial data communication. It is desirable for a PLD (which is intended to be a relatively general-purpose device) to be useful in a number of different possible applications. Indeed, as a general matter, the more possible uses a PLD can satisfy, the better (e.g., because it increases the market for that PLD product). For example, it may be desirable to provide a PLD that can support many different high-speed serial data communication protocols. Those protocols may include industry-standard protocols and protocols that a user may design on a customized basis.
High-speed serial data communication may be supported on a PLD by including on the PLD some circuitry that is dedicated to performing certain tasks associated with such communication. Such dedicated circuitry may be referred to as “hard IP” (IP being an acronym for intellectual property). The hard IP circuitry may be controllable, programmable, or configurable in some respects to adapt or customize it to particular communication protocols. Hard IP (rather than the general-purpose logic of the PLD) may be used for some aspects of high-speed serial communication for any of several reasons. These may include the need to provide higher-speed circuitry to keep up with the extremely fast bit rates of the serial communication, the large number of general-purpose logic elements that would be required to perform some of the complex encoding/decoding tasks required for some high-speed serial communication protocols, etc. Other parts of the communication task can be performed by other parts of the PLD circuitry (e.g., the so-called media access control (“MAC”) layer of the PLD and/or the general-purpose programmable logic of the PLD).
Many high-speed serial communication protocols use a coding scheme known as 8-bit/10-bit or 8B/10B coding. See Franaszek et al. U.S. Pat. No. 4,486,739, which is hereby incorporated by reference herein in its entirety. Although there is a basic 8B/10B scheme, different communication protocols may use that scheme in somewhat different ways. It is desirable for a PLD to include circuitry that supports these different versions of use of 8B/10B coding so that the PLD can be used to support a wide range of communication protocols employing such coding.